A Standard Cell-Based Frequency Synthesizer with Dynamic Frequency Counting

SUMMARY This paper presents a standard cell-based frequency synthesizer with dynamic frequency counting (DFC) for multiplying input reference frequency by N times. The dynamic frequency counting loop uses variable time period to estimate and tune the frequency of digitally-controlled oscillator (DCO) which enhances frequency detection's resolution and loop stability. Two ripple counters serve as frequency estimator. Conventional phase-frequency detector (PFD) thus is replaced with a digital arithmetic comparator to yield a divider-free circuit structure. Additionally , a 15 bits DCO with the least significant bit (LSB) resolution 1.55 ps is designed by using the gate capacitance difference of 2-input NOR gate in fine-tuning stage. A modified incremental data weighted averaging (IDWA) circuit is also designed to achieve improved linearity of DCO by dynamic element matching (DEM) skill. Based on the proposed standard cell-based frequency synthesizer, a test chip is designed and verified on 0.35-µm complementary metal oxide silicon (CMOS) process, and has a frequency range of (18–214) MHz at 3.3 V with peak-to-peak (P k-P k) jitter of less than 70 ps at 192 MHz/3.3 V. key words: frequency synthesizer, dynamic frequency counting (DFC), digitally-controlled varactors (DCV), digitally-controlled oscilla-tor (DCO), dynamic element matching (DEM), phase locked loop (PLL)